Veri cation of Synchronous Circuits by Symbolic Logic Simulation

A logic simulator can prove the correctness of a digital circuit when it can be shown that only circuits implementing the system speciication will produce a particular response to a sequence of simulation commands. By simulating a circuit symbolically, veriication can avoid the combinatorial explosion that would normally occur when evaluating circuit operation over many combinations of input and initial state. In this paper, we describe our methodology for verifying synchronous circuits using the stack circuit of Mead and Conway as an illustrative example. Logic simulators have long been used to test for errors in digital circuit designs. Typically, however, the user only simulates a limited set of test cases and assumes that the circuit is correct if the simulator yields the expected results for all cases. Unfortunately, this form of simulation provides no guarantee that all design errors have been eliminated. A successful simulation run can indicate either that the circuit design is correct, or that an insuucient set of test cases was tried. Conventional wisdom holds that simulators are incapable of more rigorous veriication. They are viewed in the same class as program debuggers{useful tools for informal testing, but nothing more. The conventional wisdom about logic simulation overlooks the capabilities provided by three-valued logic modeling, in which the state set f0; 1g is augmented by a third value X indicating an unknown digital value. Most modern logic simulators provide this form of modeling, if for nothing more than to provide an initial value for the state variables at the start of simulation. Assuming the simulator obeys a relatively mild monotonicity property, a three-valued simulator can verify the circuit behavior for many possible input and initial state combinations simultaneously. That is, if the simulation of a pattern containing X 's yields 0 or 1 on some node, the same result would occur if these X 's were replaced by any combination of 0's and 1's. This technique is eeective for cases where the behavior of the circuit for some operation is not supposed to depend on the values of some of the inputs or state variables. Using a conventional simulator, a surprisingly large class of circuits can be veriied in polynomial time (as measured in the circuit size). For example, an N-bit random access memory (RAM) can be veriied by simulating just O(N log N) patterns with